The present invention relates to a semiconductor memory apparatus, and more particularly, to an offset cancellation circuit of a semiconductor memory apparatus and a method thereof.
In a receiver circuit and a comparator circuit, which serve as chip interfaces of a semiconductor memory apparatus, offsets will undoubtedly occur due to mismatches in processes. Therefore, a typical semiconductor memory apparatus has an offset cancellation circuit for canceling the offsets occurring due to the mismatches so that the sensitivity characteristic and the resolution characteristic of the semiconductor memory apparatus can be improved.
FIG. 1 is a schematic block diagram showing a conventional offset cancellation circuit.
A conventional offset cancellation circuit 1 includes a sense amplifier 10, a control section 20 and a digital-analog converter 30. The sense amplifier 10 receives and amplifies an input signal ‘in’ and generates an output signal ‘out’.
The control section 20 and the digital-analog converter 30 function to cancel the offset of the sense amplifier 10. When the voltage level of the output signal ‘out’ is below a target voltage level, the control section 20 generates a code signal ‘code’ and provides the code signal ‘code’ to the digital-analog converter 30. In response to the ‘code’, the digital-analog converter 30 generates offset voltages ‘off+’ and ‘off−’ and provides the offset voltages ‘off+’ and ‘off−’ to the sense amplifier 10. Conversely, if the voltage level of the output signal ‘out’ reaches the target voltage level, the control section 20 maintains the count of the generated code signal ‘code’ such that the offset voltages ‘off+’ and ‘off−’ generated by the digital-analog converter 30 maintain their voltage levels. Accordingly, the sense amplifier 10 can receive with the offset voltages ‘off+’ and ‘off−’ when the target voltage level is not reaches and can generate the output signal ‘out’ without an offset.
In more detail, the control section 20 has a counter that generates a code signal that is up-counted or down-counted. When the counting operation ends, the counter generates a set signal ‘set’. The set signal ‘set’ is used in other circuits of a semiconductor memory apparatus.
Trends in the semiconductor industry are consistently moving towards high speed operation. Hence, the offset cancellation should also be quickly executed. As such, the digital-analog converter 30 should be able to quickly change the levels of the offset voltages in response to the code signal ‘code’ and should be able to maintain the levels of the offset voltages capable of canceling the offset in a stable manner. However, these two issues are in a trade-off relationship, and there is demand to simultaneously satisfy them both.